As is well known, data processing systems including microprocessors are generally equipped with various data and address registers which either temporarily store information which is to be transferred to memory in a WRITE operation or which receive information from memory in a READ operation. In some instances, it is necessary to store information into or extract information from selected ones of this plurality of registers in accordance with some predefined priority scheme.
For example, the MC68000 series of microprocessors generally available from Motorola, Inc. utilizes a "load and store multiple" instruction (MOVEM) which causes information stored in various registers in the microprocessor to be stored into memory or vice versa.
For this purpose, a multi-bit data word is constructed within the microprocessor which indicates which registers are to be manipulated and in what priority. For example, if each of the individual bits of the data word represent separate and distinct registers, then a logical one in any particular bit position may be interpreted to indicate that its associated register is to be either read into or read from.
Furthermore, the relative priority of operations associated with any one particular register with respect to the others may be determined by the relative position of its associated bit in the data word.
Thus, for example, a register whose associated bit occupies the least significant bit position of the data word may be given highest priority while one associated with the most significant bit position may be given the lowest priority.
It is necessary, however, to monitor each of the bit positions in order to detect the bit position of highest priority containing a logical one so as to perform the required operation on its associated register, the bit position containing a logical one of the next highest priority in order to perform the required operation on its associated register, and so on down the line until the correct operation has been performed on each register whose associated bit in the data word is a logical one.
A known priority encoder provides a separate channel for each bit of the binary data word whose bits it is desired to prioritize.
It is desirable to provide a priority encoder which can operate at a speed comparable to that of the other essential elements of the microprocessor, for example, the execution unit and the effective address unit. In general, the speed of a priority encoder corresponds linearly to the number of bits. Thus an 8-bit encoder runs approximately twice as fast as a 16-bit encoder. It is therefore desirable to provide a priority encoder that operates on fewer than the maximum number of bits in the data word being analyzed.
High performance microprocessors, such as Motorola's MC68000 line of microprocessors, are highly pipe-lined. That is, the microcode which controls many of their internal operations is executed in an overlapping manner rather than in a purely sequential manner. It is desirable to utilize the pipe-lining capabilities inherent in such microprocessors by providing relatively more complete control information from the output of the priority encoder than is provided by known priority encoders, which typically provide merely an indication of whether the data word being analyzed is zero or non-zero.
In addition, in the MC68040 microprocessor, the data and address registers are separated into two different execution units, namely an effective address unit and an instruction execution unit. Again, more complete control information is required to achieve optimum operation of microcode branching operations without requiring additional logic circuitry.
Therefore it is also desirable to provide as outputs from a priority encoder not only a pointer to the most significant bit which is set in the data word, but also control information in the form of an indication as to whether 1) there are zero bits set, 2) there is one bit set, or 3) there is more than one bit set. This indication can be used by microcode to branch upon the appropriate conditions.
It is also desirable to provide a priority encoder circuit which occupies a minimum of silicon area on a microprocessor chip.